makefiles containing recipes allows a faster compiling time by making sure to only re-compile changed codes. Especially if you have multiple program codes to compile, it is useful to keep the object files and link using the already compiled object files.
NOTE: You must replace the spaceholder terms. Those are such terms that are put within
>. Those brackets are not part of the syntax either.
makefile has the following syntax:
<target.o>: <dependency1.h> gcc -c <target.c> <dependency1.o>: <dependencies> gcc -c <dependency1.c> <target>: <target.o> <dependency1.o> gcc -o <target> <target.o> <dependency1.o>
You may save such a
makefile and run
make as in following:
$ make <target>
Running this command will result in an executable program that you can run via
NOTE: On some systems, it might be required to call the file
MAKEFILE instead of